The present invention relates generally to magnetic memory, and more specifically relates to hybrid magnetic memory including a magnetoresistive element and a superconducting element.
Superconducting technology such as that based on Josephson junctions has long seemed promising for implementing high-performance computer systems due to: (1) the very fast switching of superconducting elements; and (2) the low power dissipation of superconducting elements relative to semiconductor circuits (e.g., complementary metal-oxide-semiconductor (CMOS)).
The development of superconducting technology for general-purpose computing applications, however, has been largely impeded by the lack of dense, fast, and high capacity (i.e., high bit count) random access memory (RAM). Without a high capacity and low access-time memory to feed it data, a processor (especially a processor operating at the clock rates supported by superconducting logic) would be continually starved of data on which to work, thereby wasting the processor's potential computational power.
One possible solution to overcoming this lack of adequate memory in superconducting technology is to develop a hybrid chip technology, in which, for example, fast Josephson logic circuits are integrated (on the same chip) with dense memory storage elements implemented in another technology (e.g., CMOS). However, the complex level-translation circuits that are required to convert the small voltage pulses produced by the superconducting logic circuits (mV level) to the volt-level signals needed to control the memory array tend to dissipate a great deal of power and to introduce significant delay to the memory access time.
Thus, there is a need in the art for a new memory cell and array that can be interfaced with superconducting logic without complex level-translation circuits (and their associated drawbacks).